Grace and Synopsys Jointly Develop Reference Design Flow

"We chose Synopsys as our preferred EDA partner to create our first reference design flow because of their reputation in the market and their proven design solution. This relationship gives Grace and its customers a completely integrated, silicon-proven design and verification flow that will speed up product development time for complex 180 nanometer designs," said Dr. Fang Hao, senior director of Technology Development at Grace. "We look forward to working long-term with Synopsys, to help ensure that our customers get the support they need when producing the full range of advanced ICs and systems."

The flow is anchored by Synopsys' Galaxy Design platform, which includes the Design Compiler(R) synthesis tool, JupiterXT(TM) design planning tool, Physical Compiler(R) and Astro(TM) physical synthesis solutions, DFT Compiler(TM) test tool, PrimeTime(R) static timing analysis solution, Star-RCXT(TM) extraction tool, and Hercules(TM) physical verification solution. For design verification, the flow uses the VCS(R) RTL verification solution and Formality(R) equivalency checking tool from the Discovery(TM) Verification platform were also used. The reference design flow was implemented by Synopsys Professional Services, which has extensive experience creating and deploying design flows for advanced ASICs. The Galaxy Design and Discovery Verification-based flow, optimized for Grace's process technology, will help Grace's customers reduce design times, decrease integration costs and minimize the risks inherent in advanced, complex IC design.

"We're committed to working with Grace to address the needs of the growing Chinese IC market, for advanced process manufacturing capability and proven design methodologies," said Rich Goldman, vice president of Strategic Market Development at Synopsys. "Grace's advanced silicon technologies demand advanced design flows and we're honored that the company chose Synopsys Professional Services and our Galaxy and Discovery platforms to meet those demands. Our collaboration will give Grace and its customers access to a complete portfolio of the leading design and verification solutions."

"The reference design flow for Grace's 180 nanometer (nm) processes will play an active role in the commercialization of scientific research achievements. The EDA Center of Chinese Academy of Sciences will adopt this reference design flow and provide long-term technical support," said Mr. Ye Tianchun, director of the EDA Center of Chinese Academy of Sciences.

As a leading foundry in China, Grace offers customers worldwide a comprehensive set of manufacturing processes through its state-of-the-art fabs. Grace currently supports 250-nm, 220-nm, 180-nm, and 150-nm process technologies, and will soon support 130-nm.

About Synopsys

Synopsys, Inc. is a world leader in electronic design automation (EDA) software for integrated circuit (IC) design. The company delivers technology-leading IC design and verification platforms to the global electronics market, enabling the development of complex systems-on-chips (SoCs). Synopsys also provides intellectual property and design services to simplify the design process and accelerate time-to-market for its customers. Synopsys is headquartered in Mountain View, California and has offices in more than 60 locations throughout North America, Europe, Japan and Asia. Visit Synopsys online at http://www.synopsys.com/ .

About Grace

Grace Semiconductor Manufacturing Corporation (Grace) is a pure IC foundry company that specializes in integrated circuit (IC) fabrication. Grace's mission is to become a leading foundry in China by supplying high quality and advanced process technology to domestic and global customers.

Grace is located in Zhangjiang Hi-Tech Park in Pudong, Shanghai, with a total land area of 240,000 square meters and a first-phase investment of $1.63 billion. Two fabs based on 12-inch wafer specifications have been constructed. Currently, Fab 1A (8") is in full production. It will reach a monthly capacity of 27,000 8-inch wafers by the end 2004. More information about Grace is available at http://www.gsmcthw.com/ .

Forward Looking Statements

This press release contains forward-looking statements within the meaning of the safe harbor provisions of Section 21E of the Securities Exchange Act of 1934, including statements regarding the expected benefits of the joint reference design flow and benefits of the Galaxy Design Platform to joint customers. These statements are based on Synopsys' and Grace's current expectations and beliefs. Actual results could differ materially from the results implied by these statements as a result of unforeseen customer difficulties in implementing the design flow and uncertainties attendant to release of any new methodology, as well as factors described in the section of Synopsys' Annual Report on Form 10-K for the fiscal year ended October 31, 2004 filed with the Securities and Exchange Commission entitled "Management's Discussion and Analysis of Financial Condition and Results of Operations -- Factors That May Affect Future Results."

NOTE: Synopsys, Design Compiler, Physical Compiler, VCS, Formality and PrimeTime are registered trademarks of Synopsys, Inc. Astro, Discovery, Galaxy, DFT Compiler, Hercules, JupiterXT and Star-RCXT are trademarks of Synopsys. All other trademarks or registered trademarks mentioned in this release are the intellectual property of their respective owners.

CONTACT: Angela Chen of Grace, 86 21 50808888 ext. 80010, or
angelechan@gsmcthw.com, or Lynette Lu, 86 21 50808888, ext. 80016, or
lynettelu@gsmcthw.com; or Gita Rao-Prasad of Synopsys, Inc., +1-650-584-1441,
or gitar@synopsys.com

Web site: http://www.gsmcthw.com/

Web site: http://www.synopsys.com/